1. Field of the Invention
The present invention relates to the technical field of static random access memory (SRAM) and, more particularly, to an output device for static random access memory.
2. Description of Related Art
FIG. 1 is a schematic diagram of a typical dual ports SRAM and the output device thereof. As shown, for illustrative purpose, only one memory cell 100 is described, while others are schematically represented by dotted lines. The memory cell 100 consists of a plurality of metal oxide semiconductor (MOS) transistors and its output end has an N-type metal oxide semiconductor (NMOS) transistor MR. The transistor MR has a drain connected to node E of an output device 120, a gate connected to a control signal RWL (read word line) in order to control data of the memory cell 100 to be sent to node E or not. The output device 120 consists of P-type metal oxide semiconductor (PMOS) transistors 101, 103, 105 and 107 and NMOS transistors 102, 104 and 106.
FIG. 2 shows a timing diagram of the output device 120. As shown in FIG. 2, when data of the memory cell is to be read, node E of the output device 120 maintains at high potential for a pre-charging process. Accordingly, in T1 interval, signals PRE and RWL are at low potential, the transistor MR is in off state, and the transistor 101 is turned on such that a source of the transistor 101 connects to a voltage Vdd in order to precharge node E and further maintain the node at high potential. Next, in T2 interval, the potential of the precharge signal PRE changes from low to high, which represents that the pre-charge on node E is complete. Then, in the T3 interval, the potential of the control signal RWL changes from low to high, which turns on NMOS transistor MR. It represents that data of the memory cell 100 is sending to the output device 120. Next, after T3 interval, when data of the memory cell 100 is in high potential, node F of the memory cell 100 is in low potential, such that the transistor MP of the memory cell 100 is in off state. At this node, node E maintains at high potential due to the precharge. Therefore, the NMOS transistor 102 is turned on such that node G is at low potential. Next, in the output device 120, a high potential (the same high potential as data of the memory 100) on a terminal OUT is output through an inverter 122 consisting of MOS transistors 106 and 107. On the other hand, when data of the memory 100 is in low potential, the node F of the memory cell 100 is in high potential, and the transistor MP of the memory cell 100 is turned on. At this node, a source of the transistor MP is in a potential GND and it pulls down the potential on the node E. Thus, the potential on node E changes from high to low. Meanwhile, the PMOS transistor 103 is turned on such that node G is going to high potential. It induces a low potential (the same low potential as data of the memory cell 100) on the terminal OUT, which is output through the inverter 122 consisting of MOS transistors 106 and 107. However, as cited, node E connects to multiple memory cells so that the load of node E is heavy (indicated by a capacitor 108) and when a potential of node E changes from high to low, it needs more time to pull the potential down. This is why changing node G to high potential requires a long duration, which wastes time. Besides, the NMOS transistor 102 needs to be in the turn-on state as node E is in high potential, it will postpone the transistor 103 to pull the node G to high potential. Thus node G maintains at low potential when receiving the source potential of the MOS transistor 102, which causes the PMOS transistor 105 turned on. Therefore, a voltage Vdd is provided to node E through a source of the PMOS transistor 105, so that the potential of node E cannot quickly change from high to low and it wastes a long duration. Accordingly, a long switching time is required when data of the memory cell 100 sent is low potential.
Further, when a previous memory cell is read as low potential, node E is at low potential. Since the PMOS transistor 103 is turned on when node E is low potential, its source voltage is provided to node G so as to turn on the NMOS transistor 104. Therefore, a voltage GND is provided to node E through a source of the transistor 104. When a pre-charging is performed in T1 interval, node E is charged by the source voltage Vdd of the transistor 101 to high potential. The transistors 101, 104 function as shown in FIG. 3. The transistor 104 maintains node E at low potential, and conversely the transistor 101 maintains node E at high potential. Accordingly, a very small size is applied to the transistor 104 in design, which is much smaller than that to the transistor 101, thereby obtaining a higher driving force to achieve the precharge to node E.
However, by contrast, the very small transistor 104 has poorer driving capability. This may affect transmitting data of the memory cell 100 with low potential because when node G changes to high potential after a certain time waste and thus the NMOS transistor 104 is turned on to provide node E with its source voltage GND. The effect of speeding node E down to a low voltage is relatively reduced due to the cited poorer driving force. Thus, read speed of the memory cell cannot be increased.
Therefore, it is desirable to provide an improved output device for SRAM to mitigate and/or obviate the aforementioned problems.